DESIGN OF 754 IEEE BY THE MULTIPLIER OF FLOATING POINT

N. Mamatha, M. Basha, Dr.M.V. Siva Prasad

Abstract


In the computation of the data processing signal in the environment of the digitized phenomena plays a crucial role in its application include the multiplication of the floating point under the computation of the scientific research oriented strategy respectively. In terms of the computational strategy multiplications plays a crucial role in its implication of the operation of the arithmetic scenario. Here the implementation of the multiplier with the high precision of the floating point value of improvement in the speed relative to the FPGA vertex 6. And under the further research strategy there is an integration of the 754 IEEE standard plays a crucial role I the applicability by the order of design and flow handling under the conditionality of the different multiple expectation respectively. Here there is an improvement in the performance and also the storage capabilities by the present method in a well efficient way. Simulations have been conducted on the present method where it completely overcome the drawbacks of the several previous methods in a well oriented fashion respectively.

Keywords


FPGA; Verilog; Multiplier; Adder; Multiplier of floating point; Precision data; IEEE 754; Virtex 6; Clock pulse and Core multiplier respectively;

References


N. Shirazi, A. Walters, and P. Athanas, "Quantitative Analysis of Floating Point Arithmetic on FPGA Based Custom Computing Machines," Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines (FCCM"95), pp.155-162, 1995.

L. Louca, T. A. Cook, and W. H. Johnson , "Implementation of IEEE Single Precision Floating Point Addition and Multiplication on FPGAs," Proceedings of 83rd IEEE Symposium on FPGAs for Custom Computing Machines (FCCM"96), pp. 107-116,1996.

B. Lee and N. Burgess, "Parameterisable Floating-point Operations on FPG A," Conference Record of the ThirtySixth Asilomar Conference on Signals, Systems, and Computers, 2002.

Mohamed AI-Ashraf)', Ashraf Salem, Wagdy Anis., "An Efficient Implementation of Floating Point Multiplier ", Saudi International Electronics, Communications and Photonics Conference (SIECPC), pp. 1-5,24-26 April 2011.

B. Fagin and C. Renard, "Field Programmable Gate Arrays and Floating Point Arithmetic," IEEE Transactions on VLS1, vol. 2, no. 3, pp. 365-367, 1994.


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