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Vol 2, No 4 (2014): June - July 2014 DESIGN OF 754 IEEE BY THE MULTIPLIER OF FLOATING POINT Abstract PDF
N. Mamatha, M. Basha, Dr.M.V. Siva Prasad
 
Vol 5, No 3 (2017): April - May 2017 LOW POWER MULTIPLIER USING ALGORITHMIC NOISE TOLERANT ARCHITECTURE Abstract PDF
Indiga Jyothi Priyanka, K Chandra Sekhar
 
Vol 5, No 3 (2017): April - May 2017 IMPLEMENTATION OF HIGH-SPEED MULTIPLIER FILTERS USING A MODIFIED NON RECURSIVE COMMON DADA MULTIPLIER Abstract PDF
M. Kedareswararao, Padathala Kalpana
 
Vol 5, No 2 (2017): February - March 2017 AN SUPERIOR REGULATOR SCULPT WITH AUGMENTED THROUGHPUT Abstract PDF
Meda Divya Bharathi, K. Bala
 
Vol 2, No 5 (2014): August - September 2014 A HIGH SPEED BINARY FLOATING POINT MULTIPLIER FOR ALL PRECISIONS Abstract
M. Deepika, D. Jhansi
 
Vol 2, No 5 (2014): August - September 2014 DESIGN AND IMPLEMENTATION OF LOW POWER DIGITAL FIR AND IIR FILTER Abstract
P.Rajeswara Rao, K.Sanyasi Naidu
 
Vol 2, No 4 (2014): June - July 2014 DESIGN OF MAC WITH IMPROVEMENT IN PERFORMANCE Abstract PDF
N. Sharanya, L. Nageswara Rao
 
Vol 4, No 6 (2016): October - November 2016 ADOPTING ALTERNATIVE REGULATOR IN BATTERY ENERGY MODEL FOR MULTIPLIER Abstract PDF
K. Vinay Kumar, U. V.Suresh Prasad, Md. Shafi
 
Vol 4, No 5 (2016): August - September 2016 A UNIQUE MODULATOR FOR BOOST REGULATOR TO REDUCE THE VOLTAGE STRESS Abstract PDF
D. Ashok, G. Mallesh Kumar, Ashrad Mohammed, V. Harinath
 
Vol 4, No 5 (2016): August - September 2016 STRUCTURING REVERSIBLE CIRCUIT TO OVERCOME LOW-POWER DISSIPATION Abstract PDF
T. Suvarna, K. Bala
 
Vol 4, No 5 (2016): August - September 2016 DESIGNING A SWITCH FOR LIGHTER LOADS WITH BOUNDARY CONDITIONS Abstract PDF
Abhinav Ravichander, Usirikapalli Sindhu, J. Ranga
 
Vol 5, No 1 (2017): December - January 2017 EMBEDDING RESIDUE ARITHMETIC INTO MODULAR MULTIPLICATION FOR INTEGERS AND POLYNOMIALS Abstract PDF
Dr.Arvind Kundu, Mr.V.Naga Mahesh, R. Deepthi
 
Vol 5, No 1 (2017): December - January 2017 AN INTERLEAVED FED-UP REGULATOR FOR BATTERY ENERGY SOURCES Abstract PDF
T.Shiva Sai Kiran, K. Bheema
 
Vol 4, No 6 (2016): October - November 2016 DESIGN AND IMPLEMENTATION OF LOW POWER TRUNCATED MULTIPLIER BY ADOPTING ANT ARCHITECTURE USING FIXED-WIDTH RPR BLOCK Abstract PDF
K. Suresh, K. Bala
 
Vol 4, No 6 (2016): October - November 2016 ACHIEVING AMPLIFIED THROUGHPUT WITH RENOVATIVE MULTIPLIERS Abstract PDF
Ashok Reddy Padigapati, P. Osman
 
Vol 4, No 6 (2016): October - November 2016 A CLATTER LIBERAL FRAMEWORK TO CONSTRUCT REPLICA BLOCK Abstract PDF
Vinukonda Aswani, Y Mahesh
 
Vol 5, No 4 (2017): June - July 2017 DESIGN OF HIGH SPEED LESS AREA RADIX 2 AND RADIX 4 BOOTH SIGNED MULTIPLIER Abstract PDF
M. C. Konda Reddy, Mr. K. Bala
 
Vol 4, No 6 (2016): October - November 2016 BCD REPETITIVE STRATEGY TO DECREASE THE LATENCY Abstract PDF
U. Abhishek, Mrs. Y. B.T.Sundari
 
Vol 5, No 4 (2017): June - July 2017 DESIGN OF RADIX-8 MODIFIED BOOTH ENCODED BASED MODULO 2n+1 MULTIPLIER USING HARD MULTIPLE GENERATOR Abstract PDF
Jonnadula Sreenivasulu, K. Bala
 
Vol 4, No 6 (2016): October - November 2016 DESIGN OF AGING –AWARE EFFICIENT BOOTH MULTIPLIER USING ADAPTIVE HOLD LOGIC Abstract PDF
Saivalli Akondi, Nandini Medapati
 
Vol 5, No 4 (2017): June - July 2017 IMPLEMENTATION OF AREA EFFICIENT LOW POWER CMOS VEDIC MULTIPLIER USING HSPICE Abstract PDF
Jinka Nagabhushanam, N. Naga Mallikarjun
 
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