A NOVEL TECHNIQUE FOR GROUND BOUNCE NOISE REDUCTION IN DEEP SUB MICRON CIRCUITS
Abstract
As low power circuits area unit we have a tendency toll liked preferred most well-liked} currently a days because the scaling increase the leak powers within the circuit conjointly will increase chop-chop therefore for removing these quite leakages and to produce a stronger power potency we area unit exploitation many sorts of power gating techniques. during this paper we tend to area unit aiming to analyze totally different the various} varieties of flip-flops using differing types of power gated circuits exploitation low power VLSI style techniques and that we area unit aiming to show the comparison results between different micromillimetre technologies. The simulations were done exploitation Micro wind Layout Editor & DSCH software package and therefore the results got below.
References
M. Powell, S.-H. Yang, B. Falsafi, K. Roy and T. N. Vijaykumar, “Gated-Vdd: A Circuit Technique to Reduce Leakage in Deep submicron Cache Memories,” Proc. of International Symposium on Low Power Electronics and Design, pp. 90-95, July 2000.
J.C. Park, V. J. Mooney III and P. Pfeiffenberger, “Sleepy Stack Reduction of Leakage Power,” Proc. of the International Workshop on Power and Timing Modeling, Optimization and Simulation, pp. 148-158, September 2004.
J. Park, “Sleepy Stack: a New Approach to Low Power VLSI and Memory,” Ph.D. Dissertation, School of Electrical and Computer Engineering, Georgia Institute of Technology, 2005. [Online].Available http://etd.gatech.edu/theses.
S. Mutoh, T. Douseki,. Y. Matsuya, T. Aoki, S. Shigematsu and J. Yamada, “1-V Power Supply High-speed Digital Circuit Technology with Multithreshold-Voltage CMOS,” IEEE Journal of Solis-State Circuits, vol. 30, no. 8, pp. 847–854, August 1995.
N. Kim, T. Austin, D. Baauw, T. Mudge, K. Flautner, J. Hu, M. Irwin, M. Kandemir and V. Narayanan, “Leakage Current: Moore’s Law Meets Static Power,” IEEE Computer, vol. 36, pp. 68–75, December 2003.
K.-S. Min, H. Kawaguchi and T. Sakurai, “Zigzag Super Cut-off CMOS (ZSCCMOS) Block Activation with Self-Adaptive Voltage Level Controller: An Alternative to Clock-gating Scheme in Leakage Dominant Era,” IEEE International Solid-State Circuits Conference, pp. 400-401, February 2003.
Z. Chen, M. Johnson, L. Wei and K. Roy, “Estimation of Standby Leakage Power in CMOS Circuits Considering Accurate Modeling of Transistor Stacks,” Proc. of International Symposium on Low Power Electronics and Design, pp. 239-244, August 1998.
N. Karmakar, M. Z. Sadi, M. K. Alam and M. S. Islam, “A novel dual sleep approach to low leakage and area efficient VLSI design” Proc. 2009 IEEE Regional Symposium on Micro and Nano Electronics (RSM2009), Kota Bharu, Malaysia, August 10-12, 2009, pp. 409-414.
Avant! Corporation, http://www.avanticorp.com
http://www.eas.asu.edu/~ptm/
J. Shin and T. Kim, “Technique for transition energy-aware dynamicvoltage assignment,” IEEE Trans. Integr. Circuits Syst. II, Exp. Briefs,vol. 53, no. 9, pp. 956–960, Sep. 2006.
W. Cheol and T. Kim, “Optimal voltage allocation techniques fordynamically variable voltage processors,” ACM Trans. EmbeddedComput. Syst., vol. 4, no. 1, pp. 211–230, Feb. 2005.
T. Ishihara and H. Yasuura, “Voltage scheduling problem for dynamically variable voltage processors,” in Proc. IEEE/ACM Int. Symp. LowPower Electron. Des., 1998, pp. 197–202.
F. Fallah and M. Pedram, “Standby and active leakage current control and minimization CMOS VLSI circuits,” IEICE Trans. Electron., vol.E88-C, no. 4, pp. 509–519, 2005.
J. Friedrich, B. McCredie, N. James, B. Huott, B. Curran, E. Fluhr, G.Mittal, E. Chan, Y. Chan, D. Plass, S. Chu, H. Le, L. Clark, J. Ripley, S.Taylor, J. Dilullo, and M. Lanzerotti, “Design of the Power6 microprocessor,”in Proc. IEEE/ACM Int. Solid-State Circuits Conf., Feb. 2007,pp. 96–97.
S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, S. Shigematsu, and J. Yamada,“1-V power supply high-speed digital circuit technology with multi-threshold voltage CMOS,” IEEE J. Solid-State Circuits, vol. 30, no. 8, pp. 847–854, Aug. 1995.
J. Kao, A. Chandrakasan, and D. Antoniadis, “Transistor sizing issues and tool for multi-threshold CMOS technology,” in Proc. IEEE/ACMDes. Autom. Conf., 1997, pp. 409–414.
D. Chiou, S. Chen, S. Chang, and C. Yeh, “Timing driven powergating,” in Proc. IEEE/ACM Des. Autom. Conf., 2006, pp. 121–124.
A. Sathanur, L. Benini, A. Macii, E. Macii, and M. Poncion, “Multiplepower-gating domain(multi-vgnd) architecture for improved leakagepower reduction,” in Proc. IEEE/ACM Int. Symp. Low Power Electron.Des., 2008, pp. 51–56.
F. Li and L. He, “Maximum current estimation considering power gating,” in Proc. IEEE/ACM Int. Symp. Low Power Electron. Des.,2001, pp. 409–414.
H. Jiang and M. Marek-Sadowska, “Power gating scheduling forpower/ground noise reduction,” in Proc. IEEE/ACM Des. Autom.Conf., 2008, pp. 980–985.
S. Kim, S. Kosonocky, and D. Knebel, “Understanding and minimizing ground bounce during mode transition of power gating structures,”in Proc. IEEE/ACM Int. Symp. Low Power Electron. Des., 2003, pp.22–25.
Y. Chen, D. Juan, M. Lee, and S. Chang, “An efficient wake-upschedule during power mode transition considering spurious glitchesphenomenon,” in Proc. IEEE/ACM Int. Conf. Comput.-Aided Des.2007, pp. 779–782.
C. Long and L. He, “Distributed sleep transistor network for powerreduction,” in Proc. IEEE/ACM Des. Autom. Conf., 2003, pp. 181–187.
A. Abdollahi, F. Fallah, and M. Pedram, “An effective power mode transition technique in MTCMOS circuits,” in Proc. IEEE/ACM Des. Autom. Conf., 2005, pp. 37–42.
M. Anis, S. Areibi, M. Mahmoud, and M. Elmasry, “Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique,” in Proc. IEEE/ACM Des. Autom.
Refbacks
- There are currently no refbacks.
Copyright © 2012 - 2023, All rights reserved.| ijitr.com
International Journal of Innovative Technology and Research is licensed under a Creative Commons Attribution 3.0 Unported License.Based on a work at IJITR , Permissions beyond the scope of this license may be available at http://creativecommons.org/licenses/by/3.0/deed.en_GB.